Mit jelent az, hogy “Beágyazott Rendszer?” “Egy specializált számítógép rendszer, ami egy nagyobb rendszer vagy berendezés része.” Webopedia “…egy beágyazott rendszer előre definiált feladatokat teljesít, általában speciális követelményeknek megfelelve. Mivel a rendszer egy speciális feladatra készült, ezért a tervezőmérnökök optimalizálták, csökkentve a méretét és a költségeket.” Wikipedia What is embedded? (from Wikipedia) An embedded system is a special-purpose system in which the computer is completely encapsulated by or dedicated to the device or system it controls. Unlike a general-purpose computer, such as a personal computer, an embedded system performs one or a few pre-defined tasks, usually with very specific requirements. Since the system is dedicated to specific tasks, design engineers can optimize it, reducing the size and cost of the product. Embedded systems are often mass-produced, benefiting from economies of scale.

Példák beágyazott rendszerekre Just by the definition of embedded, one can think of many types of embedded applications. Today, embedded processing is a fundamental part of our everyday lives. As technology continues to expand, embedded intelligent products will continue to grow.

Az ipar legfontosabb tervezési kihívásai napjainkban A HW mérnök problémája: A komplex megoldások kihívása Ethernet, USB, video, audio, (iPod, cell phone) A SW mérnök problémája: A szoftver méret exponenciális növekedése Megközelítőleg a teljes fejlesztési költségek 50% a szoftverrel kapcsolatos A legtöbb beágyazott rendszer fejlesztése a szoftver problémák miatt késik A terméktervezési ciklus problémája: Az egyre bonyolultabb rendszerek kihívása. In the commercial industry of product design, development and deployment, one can read of the ever increasing challenges and pressures to delivering products to market. Problems limit innovation because of many reasons, some include hardware, software and the design cycle problems. No easy answer exists to reduce complexities and the pressures will never go away. However, for technology to continue to evolve, the methods and tools used to create new technologies must advance. A fundamental industry wide challenge is the limited number of persons that have the knowledge to design, build, and program embedded systems. Technology’s of today and the future do not come from the pure EE’s and CS’s engineer, but arrive by a combination of the “Domain Experts” from all science areas contributing to the product design cycle. As such, tools and methods of design that enable non embedded engineers and scientists to contribute to the design process have arrived and are continuing to grow. A second advancement that will change embedded design is the methods used for designing a product. In the next slides, information is shared on a modified design flow of the well known V-Diagram. This new design flow is often called Model Based Design. Many companies in industry say their tools are specific for Model Based Design, but that is ½ the story. Model Based Design is a universial word to describe a process for designing, testing and verifying a design with real-world parameters. As device complexity grows, as in Control, the need to use such processes is important. For a less complex embedded device, the thought process, less the actual procedures can be used to reduce errors.

A tervezési ciklus Terv Test Rendszer Specifikáció Alkalmazási teszt Kalibrálás és Funkcionális Teszt Tervezés és Szimuláció Model-based control design methods, and real-time hardware are now used throughout the design cycle for system characterization, simulation, and prototyping, moving test and implementation earlier in the development cycle, so control engineers can identify problems early and reduce risk. These model-based design tools feature built-in mathematical functions and routines optimized for designing and analyzing strategies through off-line simulation. In addition, these tools can be easily coupled with real-time hardware, supplementing traditional off-line simulation with real-world testing. This can aid in the elimination of errors early in the design, resulting in a more robust system, fewer iterations in the development cycle, and reduced development time and cost. Prototípus Rendszer Teszt (HIL) Kódgenerálás

Komplex vezérlési alkalmazások Ipari vezérlések Repülés vezérlés Precíziós gépi vezérlések Mozgás vezérlés As systems become more complex, the methods used to build embedded controllers require new design flows. As example is a control based systems. Control systems are commonly found in industrial environments. For example, consider an oil refinery with process control systems that continually manufacture and produce oil. The control system used for processing may consist of a Programmable Logic Controller (PLC) executing a PID algorithm, or a Distribute Control System (DCS) for a larger process control. In this case, the control system is used to manufacture a product. A control system can also be part of an end product being manufactured. This has been seen primarily in the automotive and aerospace industries with electronic control units and flight control systems. However, control systems are now finding their way into other end products such as precision motor controllers for computer hard drives and white goods like washing machines. While control systems used to manufacture a product often stem from established control strategies such as PID control, control systems embedded in end products often use new and innovative control strategies. The tools and techniques used to develop and embed control systems in end-products has evolved to include model-based design. However, manufacturing control engineers are also beginning to adopt these tools and techniques to develop more advanced control systems. Motor vezérlés LabVIEW in Control Design ni.com

This is an example of a common design process used to create complex embedded systems that uses model based design control algorithms.

Hogyan csökkenthetjük a beágyazott rendszerek tervezése során a komplexitást? Kulcsrakész rendszerek Moduláris redsz. Egyedi kártyák Another way to reduce design complexity and achieve time-to-market goals is to evaluate the need for Make vs Buy. When developing an embedded device, deciding which technology to implement as the system’s primary controller is one of the first key engineering milestones. In addition to considering processor architectures, operating system capabilities, and other components, you must decide which portion of the system to design and which portion to buy off the shelf. By designing and building a custom controller, you can completely customize the end solution and optimize costs, but any design specification changes or oversights very often cause lengthy and expensive delays. Alternatively, using an off-the-shelf platform increases the cost of goods sold (COGS), and you may pay for features that are not necessary for your design. Nevertheless, off-the-shelf systems typically offer a faster validation cycle and, therefore, shorter time to market. As a good engineer and business manager, it is important to look at the big picture, not just the innovation and excitement one may get starting a design from scratch. Each and every day, the combined efforts of marketing, time-to-market and design innovation are what separates product success with product failure. The next slides show an example cost comparison of Make vs Buy. This is very simplified, as one needs to look at the overall live of the product and the volume. If volume is high, the value of custom grows more important. But, do not think like many engineers and convince yourself that your product will sell millions, when it in fact probably will sell 100s. COTS kártyák Bevezetés költsége ODM kártyák Standard Silicon ASIC ASSP Gyártási volumen

Hagyományos beágyazott rendszerek fejlesztési ideje Hardver tervezés: 2 hét Logikai és áramköri tervezés: 2 hét Hardver verifikáció: 2 hét Szoftver tervezés/kódolás: 2 hét Szoftver integráció: 2 hét Rendszer teszt/ellenőrzés: 2 hét ÖSSZESEN: 12 hét, $50,000 - $150,000

Moduláris és készen kapható elemekből építhető beágyazott rendszerek Hardver tervezés: 0 hét Logikai és áramköri tervezés: 0 hét Hardver verifikáció: 0 hét Szoftver tervezés/kódolás: 1 hét Szoftver integráció: 1 hét Rendszer teszt/ellenőrzés: 1 hét ÖSSZESEN: 3 hét, $17,000 + PC költség

Általános HW rendszerarchitektúrák National Instruments Leadership Seminar April, 2002 Általános HW rendszerarchitektúrák Analog I/O Digital Sensor Bus USB, Ethernet Processor FPGA Analog I/O Digital Sensor Bus USB, Ethernet Processor Embedded system performance, price, and time to market often shape embedded system design architectures. First, Microcontroller based systems with on-board IO often solve many embedded application needs. Many also include small external memory interfaces for Flash or program data. The value in such systems is complexity is reduced, as can be costs. Limitations are performance and functionality. Second, Higher performance systems often require more complex higher precision analog to digital converters (ADC), or high-speed external communications buses such as high-speed ethernet. In these systems the IO is off-chip with connection made via common bus communication methods as SPI, parallel, or serial. Finally, Many highly complex systems today use a combination of a FPGA and Processor. The FPGA can serve many purposes: Glue logic to replace traditional TTL logic gates More complex logic decision making tasks High speed timing interface to high-speed components (ADCs, Ethernet, Custom Serial IO) FPGAs can include soft-processors, some include hard processors; (PowerPC, ARM) Limitations include higher costs, and greater configuration complexity The purpose of this training material is to demonstrate and teach you how to use the Xilinx FPGA with NI LabVIEW. LabVIEW FPGA simplifies the configuration complexity of programming an FPGA. It is a tool that also links the FPGA designers to the more traditional embedded C software engineer. Processor Analog I/O Digital Sensor Bus USB, Ethernet National Instruments CONFIDENTIAL

Általános beágyazott kommunikációs módszerek I2C SPI Serial The common communication methods used in many embedded systems in order to communicate with external devices are numberous. The most common include SPI, I2C and serial. SPI Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial busses. I2C is a multi-master serial computer bus invented by Philips that is used to attach low-speed peripherals to a motherboard, embedded system, or cellphone. The name stands for Inter-Integrated Circuit and is pronounced I-squared-C and also, incorrectly, I-two-C. As of October 1, 2006, no licensing fees are required to implement the I²C protocol. However, fees are still required in order to obtain I²C slave addresses. As the name implys serial communications is the process of sending data one bit at one time, sequentially, over a communications channel or computer bus. Many types of serial communication schemes exist and used in embedded design

Introduction to LabVIEW FPGA for cRIO 4/4/2017 2. Előadás: Téma: A. Általános FPGA programozási technikák

Introduction to LabVIEW FPGA for cRIO 4/4/2017 Tartalom FPGA műveleti paletta Egyszerű FPGA VI Párhuzamosság és megosztott erőforrások Egészaritmetikai kérdések In this lesson, we will cover the basic palette under FPGA target, the basic FPGA programming and the introduction to some of the most important concepts when programming in FPGA like Parallelism, Shared Resources and the Integer Math equations.

Introduction to LabVIEW FPGA for cRIO 4/4/2017 FPGA műveleti paletta FPGA specifikus funkciók Programozási technikák Eszköz I/O Aritmetikai és logikai elemek Tömbök és klaszterek Időzítések Matematikai és vezérlési funkciók Szinkronizálás és FIFO elemek Táblázatok The functions palette in FPGA will display only the VIs that are supported under in this environment. Many of all the LabVIEW structures, such as the while loop, for loop, and sequence structure, are supported under LabVIEW FPGA. There are also other standard LabVIEW functions for arithmetic operations, Boolean logic, timing and synchronization, a Device I/O and others.

Introduction to LabVIEW FPGA for cRIO 4/4/2017 Egyszerű FPGA VI F=(A+B)CD Programming with LabVIEW FPGA is very simple. If you have LabVIEW experience, you will have very few additional concepts to learn. The same structures and functions are used for coding. In this example, we have a simple VI where two numbers are added and multiplied to the product of two other numbers.

Introduction to LabVIEW FPGA for cRIO 4/4/2017 LabVIEW technológia leképezése FPGA-ra A megadott logika leképezése FPGA: F =(A+B)CD F AB CD The heart of RIO is an FPGA chip. You can think of an FPGA as having logic gates such as AND and OR gates that are unconnected. Your LabVIEW program is used to connect these gates and implement your logic. The process of mapping graphical code to the structure of the FPGA occurs during the compilation of a VI for the LabVIEW FPGA Module and is completely abstracted from the end user. Hardware implementations of LabVIEW’s functions are placed into the look-up tables of the FPGA and signals are routed between them as appropriate. Additional logic is used to implement LabVIEW’s dataflow.

A fordítási folyamat és a szerver Introduction to LabVIEW FPGA for cRIO 4/4/2017 A fordítási folyamat és a szerver A LV diagramok konvertálása átmeneti leíró fájlokra A leíró fájlok elküldése a fordító szerverre Lefordítja az adat fájlokat az FPGA-ra Visszaadja az FPGA konfigurációs fájlt a LabVIEW-nak A bitfolyamot egy VI tárolja A LabVIEW környezet egy kliens Tetszőlegesen kapcsolódhat a szerverhez és leválhat róla a fordítás után Once the FPGA VI is completed it needs to be compiled before it can be run on the FPGA. The output of the compile process is a bitstream which is downloaded to the FPGA. During the compile process, LabVIEW converts the diagram into intermediate VHDL files which are then passed to the Xilinx compile server. The compile server then compiles the VHDL into the resulting bitstream. Once returned, the bitstream is stored in the VI by the LabVIEW environment. The compile server is started automatically on the same computer as the development environment, however in the project options you can specify to use the compile server on your local machine or the compile server on another computer on the network. In order to use the compile server on another networked computer, the compile server must be started manually before connecting to it. This allows you to use a faster machine for compiling. Compile Server

Introduction to LabVIEW FPGA for cRIO 4/4/2017 Letöltés A RUN parancs kiadása után a fordítás végén automatikusan történik Windows OS LabVIEW FPGA Module Target FPGA FPGA VI To test and run the FPGA VI the compiled bitstream must be downloaded to the FPGA. The code is automatically downloaded when the Run button on the VI is pressed. Download Bit File Embedded FPGA VI ( a bitfájl maga)

Introduction to LabVIEW FPGA for cRIO 4/4/2017 Interaktív mód Az FPGA-n futó VI egy Előlapi panelen keresztül érhető el Nincs debug lehetőség A VI az FPGA-n fut Windows OS LabVIEW FPGA Module FPGA VI (Front Panel) Target FPGA Running the FPGA VI while targeted to the FPGA, executes the VI in interactive mode. In this mode the VI is executed on the FPGA while you see the front panel of the VI on the development machine. Updates between the front panel and the FPGA VI are handled automatically. This allows you to test the performance and behavior of the VI, though you do not have access to most of the traditional debugging tools like execution highlighting. FPGA VI (működő) Kommunikáció

Introduction to LabVIEW FPGA for cRIO 4/4/2017 Host PC interaktív mód A Host PC VI Előlapja biztosítja FPGA VI kommunikációt Megenged egyéb feldolgozást is a Host VI-ban Windows OS VI (Front Panel) Target FPGA Running the FPGA VI while targeted to the FPGA, executes the VI in interactive mode. In this mode the VI is executed on the FPGA while you see the front panel of the VI on the development machine. Updates between the front panel and the FPGA VI are handled automatically. This allows you to test the performance and behavior of the VI, though you do not have access to most of the traditional debugging tools like execution highlighting. FPGA VI (működő) Kommunikáció

Introduction to LabVIEW FPGA for cRIO 4/4/2017 Windows Target mód Windows OS Az FPGA VI a Windows rendszeren fut Szoftver emuláció Nincs hardver időzítés Debuggolás lehetséges A logika ellenőrzése fordítás előtt LabVIEW FPGA Module (targeted to Windows) You can target LabVIEW to Windows after building your FPGA VI. While target to Windows you can run the VI and test its behavior. In this mode the I/O functions do not access the FPGA hardware but return random data instead. FPGA VI

Megosztott erőforrások Introduction to LabVIEW FPGA for cRIO 4/4/2017 Megosztott erőforrások Mielőtt egy taszk használhatna egy megosztott erőforrást, meg kell várnia, míg az eszköz felszabadul. Task 1 Task 2 Megosztott erőforrás Fut Vár A Task 2 akkor indulhat, ha a Task 1 befejezte az erőforrás használatát Task 1 An important thing that affects the deterministic execution of the tasks even when they are in parallel is sharing the resources between two different tasks or loops. If these resources may only be accessed by one task at a time, they can prevent code from executing independently and are referred to as shared resources. As shown above, task 1 is running and is accessing a shared resource that can be accessed by only one task at a time. Because of this, task 2 has to wait until task 1 is done before accessing it. Once task 1 is finished, then task 2 can access the shared resource and executes and task 1 will wait for the shared resource to be free. The usage of these shared resources causes jitter. To maximize the determinism of our VI, we need to avoid shared resources Task 2 Megosztott erőforrás Vár Fut LabVIEW Real-Time Course Manual 3-22 ni.com

Megosztott erőforrások Introduction to LabVIEW FPGA for cRIO 4/4/2017 Megosztott erőforrások Megosztott erőforrások: Digitális kimenetek Memória/FIFOs Nem újra-beépülő VI-ok Lokális változók This is a list of some components that are considered Shared Resources: Digital Outputs Analog Inputs Analog Output Memory/FIFOs Non-Reentrant VIs Local Variables

Példa megosztott erőforrásokra Introduction to LabVIEW FPGA for cRIO 4/4/2017 Példa megosztott erőforrásokra This is an example that contains a shared resource. Can you find it? If you guessed the analog input function, you are correct! Analog inputs from the same channel are shared resources. Therefore, when the top loop is reading from the analog input channel, the lower loop will be forced to wait until the top loop is finished reading from that channel before it can execute.

VI-ok megosztása (nem újra-beépülő VI-ok) Introduction to LabVIEW FPGA for cRIO 4/4/2017 VI-ok megosztása (nem újra-beépülő VI-ok) Nem újra-beépülő (Alapértelmezett) A VI megosztott Egyetlen példányban épül be az FPGA eszközbe Újra-beépülő VI A diagram minden példánya külön logikai elemekre képződik le az FPGA-ban (több helyet igényel) Beállítható az erőforrás tulajdonságokban az opciók között Another common shared resource is a SubVI. By default the SubVIs are considered non-reentrant meaning that only one instance of it exists on the FPGA. This means that only one process can access that SubVI at one time. A Reentrant VI allows the VI to exist in several instances of the VI so multiple processes can access to them independently, however, this will use more space of the FPGA.

Introduction to LabVIEW FPGA for cRIO 4/4/2017 Egész aritmetika Nincs lebegőpontos művelet Sem szimpla, sem dupla pontosságban Another important caveat of using LabVIEW FPGA is there is no support for doubles or floating point data types. It does everything with integer math. As a result, some functions , such as divide, are not included on the FPGA palette. There are some ways you can implement “floating point” operations in LabVIEW FPGA that will be discussed earlier. Any floating point operations must be performed on the LabVIEW FPGA host interface VI.

Introduction to LabVIEW FPGA for cRIO 4/4/2017 Egész aritmetika Adatok skálázása A lebegőpontos szorzást/osztást helyettesítsük skálázással Leginkább 16 bites egészeknél használható, a számításoknál 32 bites szélességet használva Műveletek Szorzás egész értékű skálázó értékkel Skálázás 2 hatványaival Együttesen megoldható a szorzás törttel művelet Examples of floating point operations you may need to perform include: multiplying, dividing, or scaling a value directly on the FPGA. Due to the lack of floating point operations these are not simple to implement. A common way to perform division on the FPGA, is to use the Scale By Power Of 2 function which is essentially a multiply or divide by any power of 2. For example, if you were to use a -4 as your scale by the power of 2, you would be dividing a number by 16 (or 2 to the power of -4). Then, you can combine a multiply and a division to achieve a satisfactory scale operation for most applications. This method works best for 16-bit integers as you can convert the value to a 32-bit integer before the multiplication and use the extended number range for the product, before scaling the result back into the 16-bit integer range. Let’s look at a more detailed example.

Introduction to LabVIEW FPGA for cRIO 4/4/2017 Egész aritmetika Változó értékű skálázáshoz a skálázó faktor kiszámítható és beállítható a Host VI-ban In this example, we are scaling an analog input value, by multiplying it by a scaling factor of 11500 and then dividing it by (2 to the power of -14, or 16384). The result is a scaling value of 0.7019. Például: Skálázó faktor: 11500 Léptetés: -14 bit jobbra A művelet eredménye: 11500 / 16384 = 0.7019

Introduction to LabVIEW FPGA for cRIO 4/4/2017 Egész aritmetika A matematikai műveletek során előforduló túlcsordulások kezelésére és elkerülésére használjunk szaturációs műveleteket Túlcsordulás esetén két lehetőség van -Szaturáció -Átfordulás Saturation Arithmetic VIs also specifically help you to handle or avoid integer overflow when performing mathematical operations. You can configure these VIs to return a maximum or minimum value if an overflow condition occurs instead of performing modular arithmetic. Saturate—The VI returns the maximum numeric magnitude representable by the output data type if the actual result of the calculation exceeds the range of the output data type. Wrap—The VI returns as many of the least significant bits of the result as the output data type can hold.

Introduction to LabVIEW FPGA for cRIO 4/4/2017 3. Előadás: Téma: FPGA I/O konfigurálása FPGA I/O paletta I/O típusok

Az FPGA I/O konfigurálása Introduction to LabVIEW FPGA for cRIO 4/4/2017 Az FPGA I/O konfigurálása In order to access I/O on the FPGA, you will need to first add I/O into your project. You can do this from the project window by right clicking on the FPGA target and selecting New>>FPGA I/O. This will launch the New FPGA I/O dialog window where you can select I/O in the left hand tree and click the Add  button to add it to the project. Additionally, you can name you I/O by clicking on the default name and typing in an alias.

Introduction to LabVIEW FPGA for cRIO 4/4/2017 Az FPGA I/O használata After adding FPGA I/O to the Project, using it is as simple as dragging and dropping the I/O from the Project Window onto the block diagram. This will automatically drop the appropriate FPGA I/O node onto the block diagram. Another way to access I/O is to drop down an FPGA I/O node from the functions palette. To select your I/O you can left click the part of the FPGA I/O node that says “I/O name” and select your I/O. You can also add additional I/O to your Project from the FPGA I/O node, simply left click as mentioned previously and select Add New FPGA I/O this will launch the New FPGA I/O dialog. Az FPGA I/O kétféleképpen használható: Áthúzhatjuk a LabVIEW Project-ből Tegyünk egy üres I/O komponenst a blokk diagramba és konfiguráljuk

Introduction to LabVIEW FPGA for cRIO 4/4/2017 I/O típusok Digitális vonalak – Boole változók írhatók/olvashatók a vonalakról ADC és DAC – Magas szintű VI-ok, értékek írására és olvasására; NI R-Series hardver Előre kiosztott IO lábak az FPGA-n (pl. Xilinx Spartan 3E kártyán) Használjuk a példa projekteket mintaként There are three basic FPGA I/O types in LabVIEW FPGA hardware: digital lines, digital ports, and analog I/O. Digital lines are basic digital I/O, these lines are bi-directional on all R Series devices and some CompactRIO modules. Additional information on digital enable and digital data functionality is contained within the documentation of your specific device. On the Spatan 3E board, all lines are digital. The IO Configuration dialog groups the IO lines by on-board components. See example 2.1 The Digital Port is a group of eight digital lines. The ports use a U8 data type. One bit is used for each line. The read and write functions will take data form all lines in a given port. The analog input node reads data form the specified line(NI Hardware). The analog output node writes data to a given line. The values from the I/O lines are binary values. The binary value is based on the resolution of the board. The boards resolution is divided up into discretized values based on the range of the board. All I/O values must be converted from a nominal value to a matching binary value or vice versa to be correctly interpreted by the FPGA device.

Számláló készítése Digital I/O vonalakkal Introduction to LabVIEW FPGA for cRIO 4/4/2017 Számláló készítése Digital I/O vonalakkal A minimális használható pulzusszélességet a ciklus periódusideje szabja meg The FPGA devices do not have counter hardware built into them. All counters need to be programmed into the FPGA itself. The count register can be 32, 16, or 8 bits. It depends of the type of integer selected for the counter’s indicator. The loop period will also determine the minimum detectable pulse width. The example above has the following specs: 1 ticks per iteration in a Single Cycle Timed Loop with default 40MHz clock 25 ns to guarantee a high or low read 50 ns period = 20 MHz signals. It can read a signal at a maximum if 20 MHz. It is important to benchmark your counter before using it in a final application. Shipping examples are located in the Example Finder: Toolkits and Modules >> FPGA >> CompactRIO/R Series >> FPGA Fundamentals >> Counters

Bináris konverzió az Analog I/O vonalakkal Introduction to LabVIEW FPGA for cRIO 4/4/2017 Bináris konverzió az Analog I/O vonalakkal Az Analóg I/O használatakor a bináris értéket a nominális értékre jkell konvertálni a host VI-ban A bináris konverziós tényező az aktuális kártyától függ Spartan 3E; 14-bit ADC NI Hardware; modulonként változó The Analog read function will receive binary values which must be converted to be properly understood by an end user. For example on a 16 bit board with a range of +/- 10 V, a binary value of 65536 would correspond to +10 volts. When outputting data the same process must be implemented in order to output a binary value to the FPGA device. Because the FPGA module only supports integers all conversion must be done on the host. The conversion factor will always be dependent on the resolution of the board. Note: The cRIO modules have special calibration constants that must be taken into consideration when calculating a corresponding binary value.

Introduction to LabVIEW FPGA for cRIO 4/4/2017 3A Előadás: Téma: Digitális I/O protokollok az FPGA I/O vonalakkal

Általános digitális kommunikációs módszerek Introduction to LabVIEW FPGA for cRIO 4/4/2017 Általános digitális kommunikációs módszerek Komponens/IC kommunikáció Elektromos tervezés: SPI, I2C, JTAG, PS/2, … Rendszer kommunikáció  Repülés: MIL-STD-1553, ARINC-429, …  Autóipar: CAN, MOST, KWP, 1939, … Távközlés Űrkutatás: PCM/Telemetria Fogyasztói elektronika   Digitális audió: S/PDIF, I2S Egyedi Eszköz specifikus megvalósítás There is a wide range of communication protocols in use in systems ranging from extremely common interfaces such as RS-232 to custom protocols implemented by individual vendors and application developers. Other interfaces include SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Circuit) which are used for communication within and among electronic devices and systems. Digital communication protocols can be grouped by their application areas or industries as well as based on the nature and technical specifications of the protocol itself. We will discuss the technical details and nature of different protocols in detail in the following sections and show how LabVIEW is used to implement these. With regard to application and industry, following is basic set of categories and sample protocols that include communication interfaces that have been solved using LabVIEW FPGA Digital communication protocols can be classified based on their technical definition and requirements. This application independent way of looking at a protocol helps to focus on the details that are important in selecting the optimal implementation using the development tools at hand. Most digital communication interface fall into one of two very general categories, serial and parallel, depending on the number of data signals between a sender and receiver. If data is transferred on a single data line it is a serial data link as all data bits are transmitted sequentially or in serial. A parallel data link has more than one data line and often a multiple of eight data lines. Data is transferred in parallel, commonly one byte or word at a time. Traditionally both serial (e.g. RS-232) and parallel communication links have been used with parallel communication links offering higher data transfer rates at the same clock rate. As the bit rates that are possible on a single data line have increase into the Megabit and Gigabit range, serial links have become much more common and dominant in the market, as they provide a more cost effective solution reducing the cost of interface components (e.g. line drivers) as well as the cost of cabling. In both serial and parallel communication interfaces there may be additional signal lines used for clocking and triggering as well as control and command communication. A second basic classification of the physical communication interface is the voltage levels and ground reference that are used for the digital signal lines. Data bits and other information are transferred by the varying voltage levels of the signal lines, but there can be significant difference in the voltage levels used between different types of interfaces. In a single-ended digital signal, the voltage level of a signal line is measured relative to a common ground reference. A differential digital signal consists of two unreferenced signals and the voltage level between the two signal lines represents the signal value. Differential signals are more immune to noise picked up by the signal lines and can normally be used to transferred signals over longer distance. Specific voltage levels used in digital communication are referenced by standards such as TTL, CMOS, and LVDS and are not addressed in the protocol implementation on the FPGA. The digital inputs and outputs on the reconfigurable I/O hardware uses TTL/CMOS compatible voltage levels. If other levels are required than a signal translator/converter needs to be inserted between the interface hardware and the communication link.

Introduction to LabVIEW FPGA for cRIO 4/4/2017 I2C kommunikáció I2C is a simple, low-bandwidth, short-distance protocol. Philips originally developed I2C for communication between devices inside of a TV set. Examples of simple I2C-compatible devices found in embedded systems include EEP The two I2C signals are serial data (SDA) and serial clock (SCL). Together, these signals make it possible to support serial transmission of 8-bit bytes of data-7-bit device addresses plus control bits-over the two-wire serial bus. The device that initiates a transaction on the I2C bus is termed the master. The master normally controls the clock signal. A device being addressed by the master is called a slave.ROMs, thermal sensors, and real-time clocks. I2C is a two-wire serial bus, as shown in the slide. Each I2C-compatible hardware slave device comes with a predefined device address, the lower bits of which are often configurable at the hardware design level by grounding the lower address lines for each device address. The master transmits the device address of the intended slave at the beginning of every transaction. Each slave is responsible for monitoring the bus and responding only to its own address. The master begins the communication by issuing the start condition (S). The master continues by sending a unique 7-bit slave device address, with the most significant bit (MSB) first. The eighth bit after the start, read/not-write (), specifies whether the slave is now to receive (0) or to transmit (1). This is followed by an ACK bit issued by the receiver, acknowledging receipt of the previous byte. Then the transmitter (slave or master, as indicated by the bit) transmits a byte of data starting with the MSB. At the end of the byte, the receiver (whether master or slave) issues a new ACK bit. This 9-bit pattern is repeated if more bytes need to be transmitted. In a write transaction (slave receiving), when the master is done transmitting all of the data bytes it wants to send, it monitors the last ACK and then issues the stop condition (P). In a read transaction (slave transmitting), the master does not acknowledge the final byte it receives. This tells the slave that its transmission is done. The master then issues the stop condition.

Introduction to LabVIEW FPGA for cRIO 4/4/2017 SPI kommunikáció Pont-pont Master - Slave SPI kapcsolat SPI can achieve significantly higher data rates than I2C. SPI-compatible interfaces often range into the tens of megahertz. SPI gains efficiency in applications that take advantage of its duplex capability, such as the communication between a "codec“, or “ADC” (coder-decoder) and a processor/FPGA. SPI devices communicate using a master-slave relationship. Due to its lack of built-in device addressing, SPI requires more effort and more hardware resources than I2C when more than one slave is involved. But SPI tends to be simpler and more efficient than I2C in point-to-point (single master, single slave) applications for the very same reason; the lack of device addressing means less overhead. SPI is a serial bus standard established by Motorola and supported in silicon products from various manufacturers. Devices communicate using a master/slave relationship, in which the master initiates the data frame. When the master generates a clock and selects a slave device, data may be transferred in either or both directions simultaneously. In fact, as far as SPI is concerned, data are always transferred in both directions. It is up to the master and slave devices to know whether a received byte is meaningful or not. So a device must discard the received byte in a "transmit only" frame or generate a dummy byte for a "receive only" frame. SPI specifies four signals: clock (SCLK); master data output, slave data input (MOSI); master data input, slave data output (MISO); and slave select (ÇSS). Figure 1 shows these signals in a single-slave configuration. SCLK is generated by the master and input to all slaves. MOSI carries data from master to slave. MISO carries data from slave back to master. A slave device is selected when the master asserts its ÇSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave. These relationships are illustrated in Figure 2. The master generates slave select signals using general-purpose discrete input/output pins or other logic. This consists of old-fashioned bit banging and can be pretty sensitive. You have to time it relative to the other signals and ensure, for example, that you don't toggle a select line in the middle of a frame. Egy Master, több Slave SPI busz kapcsolat

Introduction to LabVIEW FPGA for cRIO 4/4/2017 PWM mommunikáció A PWM használható egyszerűbb szervo vezérléseknél A servo motor consists of several main parts, the motor and gearbox, a position sensor, an error amplifier and motor driver and a circuit to decode the requested position. The slide contains a block diagram of a typical servo motor unit. The radio control receiver system (or other controller) generates a pulse of varying length approximately every 20 milliseconds. The pulse is normally between 1 and 2 milliseconds long. The length of the pulse is used by the servo to determine the position it should rotate to. A RC servo is controlled by a series of pulses, wherein the length of the pulse indicates the position to take. Pulse width Angle Commit 0.6m Sec -45 degrees minimum pulse length 1.5m Sec 0 degrees center position 2.4 mSec -45 degrees maximum pulse length Notes: Increasing the pulse width by 10 µSec results in about a degree of movement on the output shaft. These numbers are nominal, and vary slightly between manufacturers and models. For example, the HiTech HS81 likes pulses between 0.74 mSec and 2.14 mSec. The rate at which these pulses are sent isn't terribly important, only the width of the pulse. Some typical rates are 400 Hz (2.5 mSec pulse spacing) and 50 Hz (20 mSec pulse spacing). The driving pulse for a common RC Servoi is usually specified as 3-5 Volt Peak to Peak. Pulzus szélesség Szög Megjegyzés 0.6 ms -45 fok minimum pulzus szélesség 1.5 ms 0 fok középállás 2.4 msc -45 fok maximum pulzus szélesség

A LabVIEW FPGA használata digitális protokollok generálására Introduction to LabVIEW FPGA for cRIO 4/4/2017 A LabVIEW FPGA használata digitális protokollok generálására Látogassunk el www.ni.com oldalra, ahol a LabVIEW FPGA-hoz különböző példamegoldások találhatók a PWM, I2C, SPI, és más protokollokhoz

4. előadás: Témák: Időzítési funkciók Ciklusvégrahajtás különböző időzítési funkciókkal Párhuzamos ciklusvégrehajtás Ciklusok szinkronizálása Adatmegosztás

Időzítési vezérlő függvények The Timing & Dialog palette contains all of the FPGA timing structures. Timing control functions are critical to your FPGA application. The timing structures include the Loop Timer, Wait, and Tick Count VI’s. The loop timer is used to control a For or While loop and set the iteration rate of the loop. This is commonly used to control the acquisition or update rate of an analog or digital I/O function. The Wait function adds an explicit delay between two operations on the FPGA. This can be used to control the pulse length of a digital output or add a trigger delay between trigger signal and resulting operation. The Tick Count function returns the current value of the FPGA clock and is used to benchmark loop rates or create your own custom timers.

Időzítő függvények konfigurálása Számolási egységek Ütemek μsec msec Belső számlálók mérete 32 Bit 16 Bit 8 Bit Each timing control structure is an Express VI that has an appropriate Configure dialog box that pops-up when you first place the VI on the block diagram or when you right click on the VI and select Properties. The dialog box allows you to configure the timing units and the size of the internal counter. The available Counter Units include ticks; a single clock cycle, the length of which is determined by the clock rate for which the VI is compiled; microseconds, and milliseconds. The Size of Internal Counter determines the maximum time the timer can track. The free running counter rolls over when the counter reaches the maximum of Size of Internal Counter specified in the Configure dialog box. To save space on the FPGA, you should use the smallest Size of Internal Counter possible for the FPGA VI.

Ciklusidőzítés A szokásosan használt ciklus szerkezetben a ciklus időzítő az első hurok végrehajtás előtt inicializálja a hurok időzítését Ha a kód végrehajtása egy esetben meghaladja a beállított időzítést, akkor a hurok időzítő ezt tolerálja és ettől függetlenül a továbbiakban is az eredetileg beállított hurok időzítést tartja. Use the loop timer function to control the acquisition rate of an analog input operation. The sequence structure controls the flow of operations in the loop. In the first iteration of the sequence, the loop timer will set a flag to mark the loop start and then the next sequence will immediately begin execution. During the second loop iteration, the loop timer will read the timestamp of the flag from the previous loop iteration and hold for the wait time to expire. If the execution of the code within the loop exceeds the loop rate defined by the timing function, then the loop timing adjusts itself for subsequent iterations.

A ciklusidő beállítás és a várakozás értelmezése A kódszerkezet teljesen azonos A ciklus időzítő kód csak az első lefutáskor aktív A várakozás a hurokvégrehajtás minden iterációjában aktív You can time your FPGA code using either the loop timer or the wait function. The difference between these two functions is how they effect code execution. When using the Loop Timer, during the first iteration the code will execute right away while with the wait, it will wait however long the wait statement is defined. For both cases, the options for choosing the timing units and the counter size are available.

Ütemszámláló alkalmazási példa: Végrehajtási idő mérése 1. Módszer 2. Módszer As we mentioned before, the tick count function is commonly used in benchmarking implementations. In these examples we present two possible methods. Using the first method, we get the current value of the FPGA clock, in the second sequence, we execute the code we want to measure, and in the third sequence we get the current value of the FPGA clock again. Knowing the tick count before and after executing the code, we can subtract both of them to find the elapsed time. Using the second benchmarking method, we use the same principle with the exception that this method is used for getting the period. Here we run the code multiple times and calculate the elapsed time every iteration.

Időzítés használata kiválasztott órajelciklushoz időzített ciklusokhoz Több funkció végrehajtása egyetlen órajel alatt A ciklus alapértelmezésben a fordításkor megadott órajel sebesség szerint hajtódik végre Javítja a kódvégrehajtás sebességét és hatékonyságát Minden kódrészletnek egyetlen órajelciklus alatt kell végrehajtódnia 50 MHz Clock = Spartan 3E HW 40 MHz Clock = NI HW 16MHz Clock = Logsys HW The single-cycle timed loop structure allows you to execute multiple functions in a single clock tick, 25 nsec for NI HW. Using the default clock, these loops run at 40 MHz. Traditional while loops in LabVIEW FPGA have 3 ticks of execution overhead, and since every function must begin on a clock edge, the functions inside the loop can add several ticks to the execution time of a loop iteration. However, in the case of a single-cycle timed loop, each function is not required to begin execution on a clock edge, but rather all functions execute as soon as their inputs become valid, and all functions complete within a single clock cycle. The code inside a single-cycle timed loop can directly interact with DIO, clock, and trigger lines of the your I/O devices, as well as the onboard RAM. Since the loop must execute in a single clock tick, some functions are not allowed. For example, any function that waits such as a loop timer or I/O method node can not be used inside the single-cycle timed loop. Analog I/O functions also cannot be used, as they require longer than 25 nsec to execute. These operations can be placed in another structure and triggered from operations inside a single-cycle timed loop.

Többszörös órajel tartományok A rendszerórajel alapján különböző sebességű órajeltartományok alakíthatók ki Ennek megfelelően a különböző egy órajelciklus időzítésű hurkok működtethetők eltérő órajelekről Támogatott I/O egységek: R sorozatú digitális I/O-k cRIO-9401 Használható: Órajelek generálására Lokális sebesség optimalizálás You can now run Single-Cycle Timed Loops at different rates using multiple clock domains. To implement multiple clock domains, you will multiply or divide the 40 MHz clock by integers between 1 and 32 to derive specific clocks. To do this, go to the Project, right click on the 40 MHz Onboard clock and select New FPGA Derived Clock. A dialog will then open to allow you to select an appropriate clock. Then you can configure a Single Cycle Timed Loop to use a derived clock by double-clicking the configuration node of the Single Cycle Timed Loop and selecting your clock. Using multiple clock domains is useful for when you need to optimize certain sections of code. For instance, consider that you have an application that has components that will only compile using the 40 MHz clock and you have a segment of code that is performing a digital edge detection operation that you want the response time to be a fast as possible. For this application, you might want to have the loop performing the digital edge detection to run inside a Single Cycle Timed Loop running at 120 MHz.

4.1 gyakorlat Téma: Időzítés és IO Tárgy: To create a VI that reads and writes to AI/O and sets a digital line high when threshold value is reached Solution: Found in Solutions folder Modify this example to use the Spartan 3E ADC and DAC.

Párhuzamos ciklus végrehajtás Előírja a ciklus végrehajtás sorrendjét Az olyan struktúrák, mint FIFO vagy eseményvezérlés képes meghatározni a ciklusok lefolyását és a végrehajtás sorrendjét Ezek a struktúrák tudják szinkronizálni a párhuzamos végrehajtású ciklusokat is Adatmegosztás Az adatok átadhatók a párhuzamos ciklusok között az FPGA-ban Használhatunk FIFO-t, memóriát vagy lokális változókat By default parallel LabVIEW loops execute independently and in parallel when implemented in FPGA hardware. In order to time loops off each other, you can effect the execution order or sequence of events so that each task is performed when desired. A structure commonly used for controlling the program flow and synchronizing parallel loops are local FPGA FIFOs. You can use FIFOs, memory, or local variables to transfer data between parallel loops.

Ciklus végrehajtási sorrend FIFO-val FPGA Az FPGA FIFO továbbítja az adatokat a párhuzamos ciklusok között A FIFO határozza meg a végrehajtási sorrendet Az adatgyűjtő beírja az adatokat a FIFO-ba A megjelenítő kiolvassa az adatokat a kijelzéshez a FIFO-ból Acquisition FPGA FIFO FPGA FIFO Indicator This diagram shows a FPGA FIFO passing data between the Acquisition loop and the Read loop. The Acquisition loop writes data into the FIFO, while the Read loop reads the data from the FIFO and displays it into an indicator. If the FIFO is empty, the read function will wait and after a specified time, it will time out and will set an output to specify that the FIFO is empty. Data Flow

FIFO-k használata adatátadásra FIFO olvasása Adatbeolvasás az eszközökről As mentioned earlier, FIFOs can also be used to pass data from one loop to another. This example shows passing calibration values from a CompactRIO module from the FPGA to the Host VI. In the top loop, we are reading the calibration values and building an array. This array is indexed through a For loop and each element is written to a FIFO. The FIFO is read in the lower loop and each calibration value is sent to the Host VI through the Calib Data indicator. The rest of the Boolean variables are used to synchronize the host and FPGA VIs. We will discuss this type of handshaking in a later lesson.

Introduction to LabVIEW FPGA for cRIO 4/4/2017 5. Előadás: Téma: A. Az FPGA VI és a gazda VI (Host VI) interfész használata In this lesson, we will cover the following topics: How to interface between the FPGA and the host VI and reasons to do so. The FPGA Interface functions palette, and the different functions inside it to: Open and close a reference to an FPGA VI Read and write values to/from the FPGA VI Control the execution of an FPGA VI using invoke nodes.

Introduction to LabVIEW FPGA for cRIO 4/4/2017 Host interfész VI-ok A felügyelő VI alkalmazás és az FPGA VI a közötti kommunikációt biztosítja Futtatható a Windows környezetben vagy a valósidejű beágyazott rendszeren Host VI FPGA VI You have seen in previous lessons how to program and compile your VIs under the LabVIEW FPGA environment. In these applications you usually have functions to perform analog input and output, digital operations, bit manipulation, arithmetic operations, Boolean logic functions, or some other algorithms. So far, to interact with the application you might have placed different controls or indicators in your FPGA VI front panel. Most FPGA applications, however, are developed so they run embedded on a RIO target, like a CompactRIO backplane or a PXI-7831R board. In these cases, you will still like to have interaction with your FPGA code, so the user can read or write values from the FPGA. This can be done by having a Host VI. A host VI can be defined as a VI that runs in software on the host computer (either running Windows or LabVIEW Real-Time) and controls and monitors the FPGA VI using the FPGA Interface functions. Some of task handled by the host VI are: File I/O: Within the actual FPGA, it is not possible to directly read and write to a file. If you need to perform file operations, for example saving the results of an acquisition to disk, you will pass the data from the FPGA to the host (either running in Windows or Real-Time) and then write that data to the disk. Display: Since the LabVIEW FPGA code is running in a headless system, you will need a host VI to display all the necessary information to the user through the configurable LabVIEW Front Panel. Networking: If the information that is being acquired or generated by your FPGA target needs to be shared between different computers, you will need to have a host VI that will act as a server to the other applications. This information can be broadcasted using different communication mechanisms like DataSocket, TCP, UPD, or via a web page. Processing: Due to the nature of FPGAs, only integer math operations are supported with the FPGA VI, like Boolean algebra or integer arithmetic operations. If you need to perform floating-point operations, like signal processing, analysis, or data-type conversions, the recommended method will be to send this information to a host VI and then send the results back to the FPGA VI. The mechanism to communicate between an FPGA VI and host VI are the controls and indicators located in the front panel of the FPGA VI.

FPGA VI interfész lehetőségek Introduction to LabVIEW FPGA for cRIO 4/4/2017 FPGA VI interfész lehetőségek To interact between your host and FPGA VI, you will use the functions located in the FPGA Interface palette. This palette installs with the NI-RIO driver; you do not need to install the LabVIEW FPGA Module for this palette to show up. However, it is important to emphasize that the NI-RIO driver will not allow you to compile or modify FPGA code, since it only allows you to download compiled code to your RIO target. While there are six functions included in this palette, the most used functions are: Open FPGA VI Reference Read/Write Control Invoke Method Close FPGA VI Reference Each of these functions will be covered in more detail throughout the next few slides.

FPGA VI hivatkozás megnyitása Introduction to LabVIEW FPGA for cRIO 4/4/2017 FPGA VI hivatkozás megnyitása Szerkesztési időben A kiválasztott FPGA VI (Target VI) vagy a bitfájl alapján határozhatók meg az elérhető vezérlési lehetőségek A kiválasztott VI a megnyitandó FPGA VI hivatkozások egy rejtett (subVI) komponense lesz Válasszuk ki a platformot Futásidőben Letölti a kiválasztott VI-t (bitfájlt) az FPGA-ra, hacsak ez már nem történt meg korábban Visszaad egy referenciát The Open FPGA VI Reference function is used to create a reference to an FPGA VI that will run or is running in an FPGA target. This function defines the bitstream that runs on the target, as well as specifies the execution target (like PXI-7831R, or cRIO-9104). There are two main purposes for this function: 1. The Open VI Reference function is used to download the FPGA bit-stream to the FPGA if it is not already on the FPGA. It will also start running the bitstream on the FPGA if it is set in the properties of the function. Note: You must compile the FPGA VI before the Open FPGA VI Reference function can download or run the VI on the FPGA target. 2. This function also provides a reference to the FPGA VI within the host VI, so that the following functions are aware of the front panel controls and indicators on the FPGA VI. It is required to call this function before trying to read or write information from the FPGA VI. During edit time, you need to configure the Open FPGA VI Reference function to specify the target FPGA VI and the execution platform. During run time, the Open FPGA VI Reference function downloads the FPGA VI bit-stream (unless it is already downloaded) and returns a reference to it. This reference is then passed to other FPGA interface functions. For additional information on the Open FPGA VI Reference function, please refer to the LabVIEW Help.

Válasszuk ki a FPGA Target VI… Introduction to LabVIEW FPGA for cRIO 4/4/2017 Válasszuk ki a FPGA Target VI… Válasszuk ki a kívánt VI-t vagy bitfájlt, amit az FPGA-ban szeretnénk végrehajtani Biztosítja a kezelőpanel vezérlő eszközeinek és státusz indikátorainak elérését referenciákon keresztül After you place the Open FPGA VI Reference function in your block diagram, you need to specify the target VI or bitfile that will run on your FPGA target. To select the FPGA VI, right-click on the function and choose Select Target VI… or Select Bitfile…. You can select the compiled VI within your project or browse and locate the bitfile; this VI will become a hidden subVI in the VI hierarchy. When the Open FPGA VI Reference function first executes on the block diagram, it checks whether the compiled FPGA VI already exists on the FPGA target. If the compiled FPGA VI is not on the FPGA target, the Open FPGA VI Reference function downloads the compiled FPGA VI to the FPGA. If you select Open and Run from the shortcut menu, the FPGA VI starts running if it is not already running; this is the default selection in the shortcut menu. To open a reference to the FPGA VI without running it, right-click the Open FPGA VI Reference function on the block diagram and select Open from the shortcut menu. You then can run the FPGA VI using the Invoke Method function. This will be covered in more detail later in this lesson.

Introduction to LabVIEW FPGA for cRIO 4/4/2017 Read/Write Control Az FPGA VI-hoz tartozó adatok küldésére, fogadására szolgál A vezérlő/kijelző elemek írása/olvasása a Read/Write Control-ban megadott felsorolásuk sorrendjében történik Komplex adatstruktúrák, tömbök, klaszterek is használhatók After a reference has been created to an FPGA VI using the Open FPGA VI Reference, you can use the Read/Write Control function to read and write the values of the controls and indicators of the FPGA front panel. To have access to the controls and indicators in the front panel of your FPGA VI, you need to wire the HW Exec Ref Out terminal of the Open FPGA VI Reference to the HW Exec Ref input of the Read/Write Control function. You can have multiple controls and indicators listed in the same Read/Write Control function; they will be evaluated in descending order as they appear on the function. One feature of the Read/Write Control function is that it allows you to access more complex data, like arrays or cluster, that are located in the FPGA VI’s front panel. You can use it to read whole clusters or an individual element of a cluster. If you need to read multiple elements of a cluster, read the whole cluster. On the other hand, you can write to a whole cluster, but you cannot write to individual elements of it. Finally, you should be extremely careful when using arrays: elements within an array are transmitted one by one between the FPGA and the Host, so transmitting large arrays might impact the performance of your system.

Close FPGA VI Reference Introduction to LabVIEW FPGA for cRIO 4/4/2017 Close FPGA VI Reference A letöltött FPGA VI-t futó állapotban tudja hagyni Le tudja állítani az FPGA VI futását After you have finished interacting with the FPGA VI, you must release the hardware resources on your host VI. The Close FPGA VI Reference is used to stop the FPGA VI running on the RIO device and close the VISA reference, cleaning up any memory used by the FPGA interface. The default behavior is Close and Abort, which closes the VISA reference and stops the FPGA VI running on the RIO target. If you only need to close the reference to the FPGA VI, but you want it to keep running (probably the VI is doing some control) you can right-click on the Close FPGA VI Reference function and select Close from the shortcut menu; this will just close the VISA reference without stopping the FPGA VI running on the RIO target.

Az FPGA VI interfészek használata Introduction to LabVIEW FPGA for cRIO 4/4/2017 Az FPGA VI interfészek használata To access and interact with an FPGA VI from a host VI using the FPGA Interface VIs follow these next steps: Place and configure an Open FPGA VI Reference function on the block diagram. Place an Open FPGA VI Reference function on the block diagram. Right-click on it and select Select Target VI… from the shortcut menu to open the Select Target VI dialog box. You should notice the FPGA VI you want to use the Project tree. Click the OK button. Right-click the Open FPGA VI Reference function and select an FPGA device by selecting Select to display the Select Board dialog box. You also can select the host computer by selecting Local Host from the shortcut menu. You should see now that the icon of the FPGA VI is placed in the Open FPGA VI Reference. Place the Read/Write Control function on the block diagram. Wire the HW Exec Ref Out output of the Open FPGA VI Reference function to the HW Exec Ref input of the Read/Write Control function. Notice that the Read/Write Control function contains one Unselected output. Left-click the Unselected output and examine the shortcut menu. The shortcut menu lists all front panel controls and indicators in the FPGA VI. Select a control available in the FPGA VI from the shortcut menu. Notice that the Unselected output changes to reflect the name of the control in the FPGA VI, and you now have an input to which you can wire a value. To write to more controls in the FPGA VI, right-click the Read/Write Control function and select Insert Control from the shortcut menu and then customize the input as described in the previous step. The read and write operations execute sequentially. Place the Close FPGA VI Reference function on the block diagram. Wire the HW Exec Ref Out output of the Read/Write Control function to the HW Exec Ref input of the Close FPGA VI Reference function.

Introduction to LabVIEW FPGA for cRIO 4/4/2017 Eseményvezérlés Futtatás Letöltés (Minden letöltés újrainicializálást okoz) Várakozás megszakítás kérésre ( IRQ ) Megszakításkérés nyugtázása IRQ If you need more advanced functionality from your host VI to interact with the FPGA you can use an invoke node. The Invoke Node is used to invoke a method or action on the FPGA VI: some of the most important uses of it is that you can start a VI running on the FPGA, stop the VI or reset the VI by forcing a download of the bit-stream to the FPGA. Here are the most common methods for an FPGA VI. You might have additional methods available depending on the FPGA device. Refer to the LabVIEW Help for further information on each method. Run: Runs the FPGA VI on the FPGA device. If the FPGA VI is already running on the FPGA device, the Run method does nothing. You will like to call this method if you just call the Open FPGA VI Reference function with the Open mode. Download: Downloads the most recent version of the compiled FPGA VI to the FPGA device. You can download an out-of-date compiled FPGA VI. If you do so, be sure the VI has the same front panel and block diagram as the more recent FPGA VI. Force Download (F) downloads the FPGA VI to the FPGA. Set the parameter to FALSE to download if the VI does not match the VI on the FPGA. Set the parameter to TRUE to download the VI every time the method is invoked. Use caution when setting this parameter to TRUE because it downloads the bitstream even if it is out-of-date. Wait on IRQ: Waits for any number of interrupt requests you included in the compiled FPGA VI running on the FPGA device. Do not call more than one Wait on IRQ method at a time per FPGA device. Always acknowledge interrupts after they occur. Use the Acknowledge IRQ method to acknowledge and reset any interrupts that occur. The use of this method will be covered in more detail in later lessons. IRQ Number(s) specifies the logical interrupt or array of logical interrupts for which the function waits. Timeout specifies the number of milliseconds the VI waits before timing out. Wire a –1 for an infinite timeout. Timed Out returns TRUE if this method has timed out. IRQ(s) Asserted returns the asserted interrupts. Acknowledge IRQ: Acknowledges and resets to default value any interrupts that occur. After a successful Wait on IRQ method, use the Acknowledge IRQ method to acknowledge the source of the interrupt. The use of this method will be covered in more detail in later lessons. IRQ Number(s) specifies the logical interrupt or array of logical interrupts the function acknowledges. Abort: Aborts the opened and running FPGA VI on the FPGA device.

Lesson 4 4/4/2017 6. Előadás: Téma: A. Az FPGA és a gazda alkalmazás közötti adatátvitel szinkronizálása In the previous lesson, we discussed how to do basic communication between a host VI and an FPGA VI. In this lesson we will explore that further and cover synchronization techniques between the host VI and FPGA VI. National Instruments CONFIDENTIAL

LabVIEW FPGA és Host kommunikáció Lesson 4 4/4/2017 LabVIEW FPGA és Host kommunikáció Az FPGA VI és a Host VI alapvetően egymáshoz képes aszinkron folyamatok Minden egyes VI a többitől függetlenül fut Az adatátvitel szinkronizálását a megvalósított alkalmazások igényei alapján kell megvalósítani Communication between the FPGA and host application consists of exchanging information and synchronizing the two applications. On their own, the VIs on the host and the FPGA VI run asynchronously. To synchronize the VIs or to use timing information from the FPGA in the host VI, you need to add code in your VIs to provide the synchronization. National Instruments CONFIDENTIAL

Aszinkron és szinkron alkalmazások Lesson 4 4/4/2017 Aszinkron és szinkron alkalmazások Aszinkron alkalmazás Az alkalmazás nem igényel kötött szinkronizálást az vezérléshez vagy az adatfeldolgozáshoz Az időzítést az FPGA biztosítja, de ez nincs szinkronizálva a Host alkalmazáshoz A beérkező legfrissebb adat mindig használható – ez általában a vezérlőalkalmazások jellemzője Szinkron alkalmazások Szoros szinkronizáció szükséges az FPGA és a Host alkalmazás között Asynchronous applications are suitable for slower control loops or control application where the synchronization of I/O and the control algorithm is not critical. For example if you run the acquisition loop at a higher rate than the control loop on your RT controller, then synchronization is not needed in most cases. You simply read the most recently acquired input value and output values from the control algorithm will be updated on the I/O cycle. National Instruments CONFIDENTIAL

Lesson 4 4/4/2017 Megszakítások Fizikai jelzést (megszakítást) generál az FPGA-tól az Host felé Egyetlen fizikai megszakítás vonal 32 logikai megszakítás Eseményvezérlés a Wait on IRQ és Acknowledge Interrupt elemekkel a Host alkalmazásban Az FPGA várakozhat a megszakításkérés nyugtázására A LabVIEW FPGA jelenlegi verzióói már támogatják a többszörös Wait on IRQ használatát, a korábbi verziók csak egyetlen IRQ várakozást támogattak. LabVIEW FPGA has the capability to let an FPGA VI generate an interrupt. This generated interrupt can be detected by a VI running on a host machine. There are 32 logical interrupts, which means that an interrupt can have an interrupt number associated with it (between 0 and 31). The interrupt is generated by the FPGA VI using the Interrupt function. A host application can use Wait on IRQ to wait for an interrupt to get generated by the FPGA VI. While waiting, that particular thread on the host VI goes to sleep. This is different than polling since it frees up the CPU for other threads. Once the IRQ is received by the host application, it can choose to acknowledge it using Acknowledge Interrupt. When the FPGA VI generates the interrupt using Interrupt, it can be configured to Wait Until Cleared. This means that once an interrupt is asserted, the FPGA VI waits until the host VI acknowledges the interrupt using the Acknowledge Interrupt function. National Instruments CONFIDENTIAL

Megszakítások FPGA – IRQ beállítása Lesson 4 4/4/2017 Megszakítások FPGA – IRQ beállítása A megszakítás logika beállítása az FPGA blokk diagramban (IRQ Bit) Opcionálisan az FPGA blokk diagramban beállítható várakozás a Host alkalmazástól érkező nyugtázásra, ami törli a kérést Set IRQ - Asserts an interrupt on the interrupt line of the FPGA device. Wait on IRQ - Host function to wait for an interrupt. The Wait on IRQ function puts the LabVIEW thread to sleep so that the RT controller can process data in other LabVIEW threads while waiting for the interrupt. The function can be configured to wait for one or more of the 32 possible logical interrupts. The actual logical interrupt asserted is returned from the function. National Instruments CONFIDENTIAL

Megszakítások Host – Wait on IRQ Host – Acknowledge IRQ Lesson 4 4/4/2017 Megszakítások Host – Wait on IRQ Specifikálja a várt logikai megszakítás kéréseket Visszaadja az aktuális logikai megszakítás-kérések azonosítóit A szálak inaktívak (sleep) a várakozás ideje alatt Több Wait on IRQ is használható a Host VI-ban Host – Acknowledge IRQ Törli az IRQ Number(s) által megadott logikai megszakításkéréseket A megszakításkéréseket mindig nyugtázni kell, még akkor is, ha az FPGA nem várakozik a nyugtázó jelre The host application needs to acknowledge every interrupt received from the FPGA. This call includes the logical interrupt number of the IRQ received and should be wired from the output of the Wait on IRQ function. National Instruments CONFIDENTIAL

RIO/Host szinkronizáció Lesson 4 4/4/2017 RIO/Host szinkronizáció FPGA VI biztosítja a felhasználói felületi kezelőszervek és kijelzők be/kiviteli adatforgalmát Host VI várakozik (sleeps) az IRQ kérés beérkezésére FPGA VI-tól FPGA VI beállítja az IRQ 0 kérést Host VI azonnal felébred amint érzékeli a beérkező IRQ-t azFPGA VI-tól FPGA VI várakozik az IRQ nyugtázására Host VI-tól Host VI leolvassa ill. frissíti az előlapi objektumokat az FPGA VI-ban Host VI nyugtázza a IRQ 0-t FPGA VI felébred és befejezi az iterációt 5. A fenti lépések ismétlései 3 4 1 Host 2 FPGA 1 This is an example of synchronization between the FPGA and host application implemented using interrupts. In this case an interrupt is asserted for every I/O operation on the FPGA. When the IRQ is received by the host it reads the most recent analog input value from the FPGA, runs the PID algorithm and then updates the FPGA with the next analog output value. Because the host application waits for the interrupt from the FPGA, the timing of the loop on the FPGA controls the timing of the loop on the host and the two loops are synchronized. 3 4 National Instruments CONFIDENTIAL

DMA adatátviteli módszerek Lesson 4 4/4/2017 DMA adatátviteli módszerek Megjegyzés: Ez a fejezet csak az NI R-Series FPGA HW-re vonatkozik. Blokkoló átvitel Lekérdezés Megszakítás Now we will learn different methods for transferring data using DMA. These are the blocking method, polling method, and interrupt method. National Instruments CONFIDENTIAL

DMA (Blokkoló módszer) Lesson 4 4/4/2017 DMA (Blokkoló módszer) A legegyszerűbb megvalósítás Egy adott időkorlát (Timeout) figyelembevételével az előírt számú adatot próbálja beolvasni Ez a módszer processzor intenzív, de nagyon gyors The blocking method is the simplest implementation method. Here, the host will wait until the specified number of elements are available before the timeout expires. Once the specified number of elements are available, they will be read into the host VI. This method, while simple and very fast, is the most processor intensive. National Instruments CONFIDENTIAL

DMA (Lekérdezéses módszer) Lesson 4 4/4/2017 DMA (Lekérdezéses módszer) Ez a módszer először egy DMA-val lekérdezi az elérhető adatok számát, majd egy következő DMA-val beolvassa az adatokat A módszer kevésbé processzor intenzív, de azért gyors The polling method uses less of the processor resources by making two DMA FIFO reads. In the first loop iteration the DMA FIFO read determines how many elements are remaining in the DMA FIFO and then passes that information to the DMA FIFO read in the next loop iteration. The DMA FIFO read then reads in the amount of data specified each iteration while programmatically determining how much to data to read for each successive loop iteration. Since the host application does not simply wait for the DMA FIFO to fill up, this method is less processor intensive, but it is not as fast as the blocking method. National Instruments CONFIDENTIAL

DMA (Megszakításos módszer) Lesson 4 4/4/2017 DMA (Megszakításos módszer) A megszakításos módszer egy IRQ kéréssel jelzi az FPGA-ból ha adott számú minta elérhető a FIFO-ba A Host várakozik az IRQ-ra és fogadva a kérést kiolvassa az adott számú mintát Ez a módszer nem terheli a processzort, de lassabb The interrupt method is very similar to what was shown in slide 10. However, this is used for applications requiring larger data transfers. Here the interrupt will be used to signal when a number of samples have been put into the FIFO. The host will wait for the interrupt and once the interrupt is read, will read in a specified number of elements. This method is even less processor intensive, but is the slowest of all three methods. National Instruments CONFIDENTIAL

7. Előadás: Téma: Teljesítmény elemzés A LabVIEW leképezése az FPGA-ra Sebesség optimalizáció Erőforrás optimalizáció

A VI-ok ciklusidő elemzése 1 ütem = 1 órajel ciklus Az órajel ciklus ideje fordítási paraméter (Alapérték a HW rendszertől függ NI 40MHz, LOGSYS 16MHz) A 32 bites számláló az órajel felfutó élére lép A Tick Count függvény visszaadja a számláló értékét What is a tick?

A VI-ok ciklusidő elemzése Minden iterációhoz időbélyeget rendelünk Kiszámítjuk az időeltérést A méréseket a ciklusvégrehajtással párhuzamosan végezzük* A tesztelő kód később eltávolítható The Tick Count VI can be used to benchmark you application as well as create custom timing VIs. Here we see an example of how the tick count is used to benchmark the execution period of a looping structure. *kihasználjuk az FPGA előnyét a párhuzamos végrehajtáshoz

A VI-ok ciklusidő elemzése Olvassuk le a kezdeti időt Hajtsuk végre a ciklust Olvassuk le a befejezési időt Számoljuk ki az időkülönbséget A mérés párhuzamosan történik* A kód később eltávolítható Here the Tick Count is used to benchmark a frame of code. *kihasználjuk az FPGA előnyét a párhuzamos végrehajtáshoz

A VI-ok erőforrásigény elemzése Sebesség Az elméletileg elérhető maximális sebességet (Theoretical maximum) is leolvashatjuk Erőforrásigény IOBs – Input/Output interfészek MULT18X18s - szorzók SLICEs – Konfigurálható logikai elemek, azaz LUT-ok és FF-ok BUFGMUXs – az órajel hálózatokat meghajtói After compiling, a report is generated which provides information on speed and size of the compiled VI. The Device Utilization summary provides information on the number of SLICEs used. This metric is the most important measure of your programs size in hardware. The design process should be an iterative process. During the process you will notice the SLICEs used will most likely increase as your program gets larger. You must be aware of what operations you have added if you notice a significant increase in SLICEs used.

Ha esetleg túl nagy vagy túl lassú…. Módosíthatjuk a kódot a sebesség, az erőforrásigény vagy akár mindkét paraméter javítására Ebben nagy segítséget jelent, ha megértjük, hogyan képezzük le a LabVIEW elemeit az FPGA-ra

A LabVIEW leképezése az FPGA-ra Az adatfolyam fenntartásához három komponens szükséges A megfelelő logikai függvényeke Szinkronizáció Engedélyezési lánc LabVIEW executes code in a dataflow manner. Nodes execute when data is present on all of the nodes inputs. When the node finishes execution the outputs of the node pass data to the next node downstream. LabVIEW FPGA uses 3 components to maintain this dataflow paradigm. First the node has logic corresponding to its function. In this figure we see the boolean not function and its associated logic. The next component needed for dataflow is synchronization. This component registers the outputs of the function in order to isolate the logic from timing uncertainties. Finally additional logic referred to as the “enable chain” is used to coordinate the dataflow by validating the inputs and outputs. What is a register (FF)? Passes data from input to output on rising edge of clock. Synchronous because everything runs off of same clock.

Az adatfolyam fenntartása az FPGA-ban FFs FFs FFs Here is a simple VI that has a boolean control and not function and a digital output function. Let’s step through the functions to see how this would be transformed for the FPGA. The boolean control has some logic associated with the data register to retrieve data from a host application. There is also a FF used as a link the enable chain. The not function has the logic associated with the function itself, a synchronization FF, and a enable chain FF. The digital output has a synchronization FF and an enable chain FF as well. Let’s examine how stringing this logic together would execute. When the program is run the enable line goes high. This enables the synchronization FF associated with the boolean control. Meanwhile a rising edge of the clock pushes the data from the register through the FF. Downstream the previous values are held on the outputs of the FFs. During the next rising edge of the clock the synchronization FF associated with the not function passes the new value through. Downstream the dio is still held at the initial value because the enable in on its FF is still low. On the third rising edge of the clock the enable in of the digital output is high and the new value is pushed through the FF to the I/O pins. Lets abstract all the logic that is actually implemented and just call them FFs. Lets see where these FFs get placed. This data is synchronized using a FF that pushes the data through the FF on the first rising edge of the clock. But in reality, most of our application involves run code repeatedly. So lets now look at how dataflow is enforced in a LVFPGA loop architecture. As we are familiar with, this kind of architecture is usually implemented using WHILE loop

A sebesség optimalizálása Párhuzamos ciklusok Pipe-line végrehajtás Egy óraütem alatt végrehajtott ciklusok Példák

Párhuzamos végrehajtás A grafikus programozás jól támogatja, sőt ösztönzi a párhuzamos kódfelépítést A LabVIEW FPGA igazi párhuzamos végrehajtást valósít meg Using the parallel nature of graphical programming and the truly parallel implementation on the FPGA you can separate your code into different code segments which can run in parallel and achieve a faster loop rate than when everything is in one process. As you develop your code start thinking about logical pieces to break the code into different segments.

Példa párhuzamos végrehajtásra 37 Ticks ~ 1uSec A ciklus sebességét a leghosszabb végrehajtási idő korlátozza AO0 végrehajtási ideje 35 ütem, DIO0-é pedig 1 ütem (ezek HW specifikus adatok) Válasszuk szét a két funkciót Így DIO0 függetlenül futhat AO0-tól Ez megengedi DIO0 mintavételezési sebességének növelését közel 10x-re a független ciklusban 4 Ticks ~ .1 uSec

Pipe-line végrehajtás A ciklustörzsön belül a kód felosztható különböző iterációkba ami lényegesen csökkentheti az egyedi iterációk hosszát Az adatfolyam különböző részeit párhuzamosan kezelhetjük egyetlen iterációban Az adatokat a következő iterációnak shift regiszterrel vagy visszacsatoló pontokkal adhatjuk át Pipelining is the process of breaking up code within a loop and dividing it up into different iterations of the same loop. Therefore the length of the data flow process within one loop iteration is reduced and the loop can run faster while executing the same code in parallel. The diagram illustrates how a process consisting of A and B can be broken up and run in parallel to reduce the length of each loop iteration.

172 órajel ütem (4.3 μs) ~ 19%-kal gyorsabb Pipe-line példa Example showing how pipelining the analog input and output operations drastically reduces the loop period, increasing the sample rate or control loop rate. Since the analog input and analog output operations both take a long time to run on the FPGA it is very efficient to put them in parallel on the FPGA and have them run at the same time. 212 órajel ütem (5.3 μs) 172 órajel ütem (4.3 μs) ~ 19%-kal gyorsabb

Egy óraütem időzítésű ciklusok (SCTL) A ciklus törzs végrehajtható egyetlen órajel ütem alatt Minimalizálja a szinkronizáció és az engedélyezési lánc által igényelt vezérlési többlet hardvert Azonban vannak korlátozások Bizonyos típusú VI-ok és függvények nem használhatók ezekben a ciklusokban Egymásba ágyazott ciklusok Megosztott erőforrások Bármi, ami egy órajlenél több időt igényel a végrehajtáshoz The Single Cycle Timed Loop (SCTL) is a special form of the While loop available on the FPGA. It uses the same representation as the timed loop on the Windows or RT target, but has little in common with that structure. Conceptually it is a While loop that runs in one clock cycle of the FPGA for each iteration of the SCTL. Thus the loop rate of the SCTL is the same as the clock frequency of the FPGA. This of course offers us great benefits with regards to the performance of our VIs, executing code extremely fast. In addition the code generated by the compiler from the SCTL is more optimized and takes up less space on the FPGA compared to the same code inside of a regular while loop. So why wouldn’t you always use the SCTL? There are some significant limitations to the use of the SCTL I your application. To use the SCTL all operations inside the SCTL must fit within one cycle of the FPGA clock. This is determined by the code generator before starting the compiler. The code generator will give an error message if the SCTL can not generate the proper code for the compiler. You can use the pipelining technique to reduce the length of each run through the SCTL by breaking up the code among multiple iterations of the SCTL. In addition to pipelining, you can use a State machine within the SCTL to better organize your code and run through a sequence of steps. The basic component of the state Machine is a Case structure with each containing one state and using a shift register to determine the next state after each iteration of the loop. Of course each state must be able ti run in one clock cycle. Using shift registers and a counter value you can implement the functionality of a For loop or add a specific number of Wait states to your program execution. Ciklus időzítés Várakozás

SCTL példa A kód áthelyezésével az SCTL ciklusba 5 órajel ütem sebességjavulás érhető el Example of the SCTL to perform some data processing within one clock cycle. The same operation in a While loop would require about 6 clock cycles including the overhead of the While loop. The SCTL also removes the enable chain overhead and therefore uses less FPGA slices. As shown the SCTL uses 5% less slices than the code outside the SCTL. 6 ütem 512 Slices 1 ütem 454 Slices

A ciklus végrehajtási idő javítása Mit tehetünk a lassú a végrehajtás? 12 órajel ütem 1 2 3 4 5 6 7 8 9 10 11 12 FFs The longest path is from the DIO to the position indicator. Very little is done in parallel.

Csökkentsük a leghosszabb adatút hosszát Alakítsuk át a blokkdiagramot 9 órajel ütem 1 2 3 4 5 6 7 8 9 FFs We just took advantage of parallelism. What about pipelining?

Alkalmazzunk pipe-line megoldást 1 2 3 4 5 6 Figyeljük meg a pipe-line hatását 6 órajel ütem FFs Further reduced by pipelining. Need to remember that the position indicator is from the previous iteration of the loop.

Használjuk az SCTL típusú egy órajelütem alatt végrehajtott ciklust Szükségtelenné teszi a szinkroizációhoz és az engedélyező lánchoz kapcsolódó logikát 1 órajel ütem 1 The single cycle loop has removed the synchronization and enable chain. The operations inside the loop can all take place within 1 clock cycle. We will see that the SCTL can also be used for size improvements because of the removal of the enable chain logic. FFs FFs FFs FFs FFs

Erőforrás optimalizáció SubVI-ok Felhasználói felület objektumok Adattípusok Függvények, amik sok helyet foglalnak SCTL- Egy órajel ütem alatt végrehajtható ciklusok Példák Another major constraint of the FPGA is the limited number of gates on the device. The techniques in the list will be investigated to help reduce the size of a FPGA program.

SubVI-ok megosztása A nem újra beépülő subVI-ok alapvetően megosztott komponensek Lassabb végrehajtás Kevesebb erőforrás (általában) Újra beépülő subVI-ok minden példánya új logikai elemeket generál Gyorsabb végrehajtás Több erőforrás (általában) Example of maintaining state information in the main VI and passing it into a subVI. Újra beépülő Nem újra beépülő Szorzók száma (MULT18X18) 18 a 40-ből 45% 3 a 40-ből 7% SLICE.ok száma 2116 a 5120-ból 41% 2028 a 5120-ból 39%

Csökkentsük a Front Panel Objektumok számát (FPO) Extra logikét igányel az adatátvitel vezérlése a host és az FPGA között A Front Panel Array-k különösen költségesek Csökkentsük a tömbök méretét Az adatokat inkább tároljuk a felhasználói memóriában When optimizing your code for the amount of space it uses on the FPGA, you should consider the front panel controls and indicators you are using. Each front panel object and the data it represents takes up a significant portion of the FPGA space. By reducing the number of these objects and reducing the size of any arrays used on the front panel you can significantly reduce the FPGA space required by the VI. Instead of creating large arrays to store data and transfer it to the host application, store the data in user memory from you FPGA VI and transfer it in smaller blocks to the host application.

A Front Panel Array hibás használata adatátvitelre Ez a diagram egy kezelőlapi tömböt használ az adatátvitelhez a host felé When optimizing your code for the amount of space it uses on the FPGA, you should consider the front panel controls and indicators you are using. Each front panel object and the data it represents takes up a significant portion of the FPGA space. By reducing the number of these objects and reducing the size of any arrays used on the front panel you can significantly reduce the FPGA space required by the VI. Instead of creating large arrays to store data and transfer it to the host application, store the data in user memory from you FPGA VI and transfer it in smaller blocks to the host application.

Egy jobb adatátviteli módszer Használjunk skaláris adatokat az FPGA memória és a host közötti adatátvitelhez When optimizing your code for the amount of space it uses on the FPGA, you should consider the front panel controls and indicators you are using. Each front panel object and the data it represents takes up a significant portion of the FPGA space. By reducing the number of these objects and reducing the size of any arrays used on the front panel you can significantly reduce the FPGA space required by the VI. Instead of creating large arrays to store data and transfer it to the host application, store the data in user memory from you FPGA VI and transfer it in smaller blocks to the host application.

Használjuk mindig a legkisebb megfelelő adattípust

Tömörítsük az adatokat becsomagolással Egyesítsük a kisebb méretű adatokat egyetlen 32 bites formátumba Csökkenti az előlapi objektumok számát Gyorsabb adatátvitel az FPGA és a Host között Split Number

Erőforrásigényes funkciók Hányados / Maradék képzés (Osztás) Szorzás helyett skálázzunk 2 hatványaival (a konstans értékű hatványozás költségmentes) Tömb funkciók (használjunk konstansokat ahol lehetséges)

Egyetlen órajelnyi időzítésű ciklusok Eltávolítja az engedélyezési lánc által okozott extra logikát FFs FFs FFs FFs FFs FFs FFs FFs FFs FFs FFs FFs FFs FFs

Erőforrás optimalizálás Ez a VI túl nagy lesz a szintézis után. Miért? This VI uses an array to store sinewave data. The array is indexed to get a value. In addition, four previous points are stored in shift registers. The previous four values are averaged. This VI is too large to compile. What can be done to help optimize this code?

Erőforrás optimalizálás Ez a VI az 1M kapus FPGA 21%-át elfoglalja. Lehetne kevesebb is? We have replaced the array with a lookup table. This change alone has allowed us to compile the program and use only 18% of a 1 million gate FPGA. Can we further optimize the program? Hint: what primitives use a large amount of FPGA space? Number of SLICEs 1090 out of 5120 21%

Erőforrás optimalizálás Ez már csak 9%-a az FPGA elérhető erőforrásainak. Lehetne még jobb? We have removed both Quotient Remainder (QR) functions. One of the QR functions was being used to index through the lookup table. This was replaced by a shift register counter operation. This shift register counter operation is a very common technique in FPGA. The other QR function was replace by a scale by 2 to the power of n. Because the scale by 2 has a constant input it uses very little FPGA space. Note: Scale by 2^ -2 is equal to dividing by 4. Can we do better? Number of SLICEs 511 out of 5120 9%

Erőforrás optimalizálás Ez már csak az FPGA 8%-a. The design was modified to use a SCTL. We added a shift register counter to replace the function of the loop timer. This new counter in combination with the case structures make only certain code execute at a specified rate. Every 5000 iterations the index register will increment and new values will be pushed into the averaging shift registers.